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Inviata - 29/09/2018 : 05:04:22 The [url=https://www.omc-stepperonline.com/steppermotor]stepper motor[/url] behavior belonging to the MC is not consistent which is affected by the Swiftness switch setting. Next week we will probably connect a logic analyzer for the CM Flip-Flops to guarantee that everything is doing the job correctly. We also should determine why the CM is not getting a response from your Core Memory Controller.
01/12/13 The Mode Info flexprint cable #26 that goes through the front panel to position CP H36 had peeled separately. I replaced the flexprint using [url=https://www.omc-stepperonline.com/steppermotor]stepper motor[/url] modern ribbon cable as the signals in the cable television are static. The PERFORM STEP, SING INST, plus REPT lights work now.
We ran the maintenance test described in sections 3. 7. 7. 3 belonging to the PDP-9 maintenance manual. To start the diag you click the I/O RESET switch, turn the console REPT move on, set the maintenance switch while in the MAINT position, and latch the beginning switch up. The contents of this AR register are copied to [url=https://www.omc-stepperonline.com/bldc-motor/]brushless dc motor[/url] each of the other registers. You implement the REGISTER DISPLAY switch to determine the contents of your registers. The contents belonging to the AR go onto this A bus, are tell you the ADR to increment internet, and then onto the O bus, and into the MB. The contents belonging to the MB go onto this B bus, the B bus masters the ADR, and on to the O bus. The O bus is loaded into the AC, AR, [url=https://www.omc-stepperonline.com/bldc-motor/]https://www.omc-stepperonline.com/bldc-motor/[/url] and PC registers. It would also procede with going into the MQ register if this technique had the EAE. The contents of this address switch register can also be inclusive-ORed with the ADR. All this behavior looks OK, making sure that means that large regions of this system are dependable, especially the Control Recollection. See page D-BS-KC09-A-10 CM Clock, Run, and Display (Sheet 1). We looked over the A, B, and C flip-flops throughout section D2 & D3 for the [url=https://www.omc-stepperonline.com/nema-17-stepper-motor/]nema stepper motor[/url] reason that control much of your CP timing. The REPT CLK interval is 8 uS, TWENTY EIGHT uS, 200 uS, 2. 6 mS, and 40 mS for switch options of 5-1. This is towards the values in the table on page D-BS-KC09-A-10 CM Time, Run, and Display Timing. The top trace is a REPT CLK. The bottom trace is a flip-flop C(0) output with pin J. The period from the REPT CLK is 200 uS so the REPT SPEED switch [url=https://www.omc-stepperonline.com/nema-17-stepper-motor/]nema stepper motor[/url] has been set to position THREE OR MORE. This looks OK, plus was also OK during other speed settings. There seemed to be no output on pin J if the processor was running. That is OK.
The top trace is a flip-flop C(0) output with pin N of flip-flop B. Underneath trace is the flip-flop B(0) result on pin P. The period of the C(0) is around 18 uS so the particular REPT SPEED switch had been set to position 5 [url=https://www.omc-stepperonline.com/cnc-kit/]cnc router kit[/url] VARIOUS. The output of this B flip-flop has glitches if the input signals change. Many of us swapped the S206 modules in slots J29 & J30. There seemed to be no change in this behavior. We need to solve this or the CP timing shall be really confused.
The A long time Meter showed 40181. 9 when you finished. 01/19/13 EXAMINE and DEPOSIT will not be working. We need to determine if that is a processor or memory difficulty. We spent some longer [url=https://www.omc-stepperonline.com/cnc-kit/]cnc router kit[/url] looking at the system's behavior when its doing an EXAMINE. We're actually getting three CM CURRENT pulses, not just two as we originally though. One was 5uS prior to a other two when were running in a slow speed, so we didn't see it about the 'scope. The first CM expression has the SM bit started so it will wait to synchronize while using core memory controller the right time. The second and lastly words run asynchronously while using core memory controller.